Hardware / Software Codesign for Platform FPGAs

System-on-a-chip FPGAs including embedded processors (hard or soft), busses, memory and hardware accelerators provide an opportunity for system designers to develop high performance, optimal systems. However, to realize the promise of this vision, a complete tool chain from concept to implementation is required. We describe an automated design framework that enables development of hardware / software FPGA systems starting with a pure, ANSI-C design specification. Profiling and analysis assist the developer in determining the hardware / software partition while a suite of verifications technologies including functional, cycle accurate, timing accurate and hardware-in-the-loop assist in system verification. Finally, advanced compilation technologies, including an optimized C to hardware compiler, provide a full push-button implementation flow. Introduction / Background The constant drive to provide more functionality, performance and flexibility for embedded applications is stressing the limits of traditional design and development approaches. As we attempt to squeeze more performance out of embedded processors, we run into limitations on throughput and performance based on system bottlenecks, architectural constraints and memory or interface bandwidth. Figure 1: Typical embedded computational system: microprocessor, memory, IO Assuming that the IO is sufficient to meet throughput requirements, then a number of items typically become system bottlenecks: processor speed, memory bandwidth, bus architecture. Embedded CPU PERIPHERAL BUS UART GPIO ETHERNET MEMORY CONTROLLER MEMORY